This invention relates to data processing electronics in general and more particularly to memory access techniques.
The development of the microcomputer and microprocessor or central processing unit (CPU) is essentially a history of technological advancement in increasing speed, accuracy, reduction in size and power of the various CPUs as they have evolved.
Throughput is a measure of the efficiency of a system or the rate at which the system can handle work. The speed at which problems or segments of problems are performed in a computer varies from application to application, and is meaningful only in terms of a specific application. Therefore, an increased throughput must necessarily consist of a comparison between the older slower method and the newer faster method while performing the same application.
Various methods of increasing throughput in given applications have been tried including pipelining as used in a "vector processor" such as the Texas Instruments Advanced Scientific Computer (ASC), the Control Data Corporation String Array Processor (STAR), and the Cray Research Corporation Cray 1. These machines utilize a technique for speeding up the throughput by having a plurality of stages perform one independent task on the instructions and then pass the instruction to the next stage for further processing. This is particularly applicable with a vector or matrix operator, hence the name "vector processor". This architecture, however, is prohibitively expensive in most applications and requires a significant hardware overhead.
A second type of pipelining is described in the Advanced Microdevices pamphlet entitled "Build a Microcomputer", Chapter II, page 23, which is incorporated herein by reference, where a pipeline architecture is described as overlapping the fetch of the next microinstruction while executing the current microinstruction. This is achieved by inserting additional registers in the overall path such that the signals can be held step by step. The advantages of this technique, however, are offset by the disadvantages of a relatively complex hardware system, particularly when the problem sought to be overcome is merely a memory access time slower than the optimum speed which the CPU is capable of handling. A second drawback is that the register described in that pamphlet is required as a component for machine operation, rather than merely an additional register added as desired for speed improvements.
An alternative method that may be used to increase throughput (as well a minimizing connections between the CPU and memory) is represented by the F-8 microprocessor family of devices manufactured by Fairchild. That throughput enhancement technique utilizes a hardware organization significantly different from typical CPU organization and requires the inclusion of addressing registers (program counter and data counter) and incrementers on the memory devices. Each memory device in the system must contain such registers, since the traditional address bus that typically links the CPU with memory is missing from the F-8 architecture.
A yet further alternative is the utilization of a cache or virtual memory system in a main-frame architecture utilizing a double or triple level hierarchy memory where the first level of memory is directly addressable by the CPU and is normally a fast memory as compared to a slow second level hierarchy main memory which is utilized for bulk memory storage and is normally not directly addressable by the CPU. In operation, the cache system addresses words or pages which have a probability of being required by the CPU and they are temporarily stored in cache. When the CPU calls for an address which is in cache, the memory response time is thus greatly enhanced; however, when the address is not in cache, the memory access time is the same or somewhat slower than the normal main memory access time. A number of algorithms for cache control have been developed and terms such as "hit ratio" refer to the algorithm's probability of success of providing a required address in cache to the CPU as compared to not having a required memory word in cache. Once again, however, these architectures (double or triple level hierarchy), are relatively expensive and are only justified in large relatively complex systems.
Additional methods of memory access speed-up related to computer architecture are discussed in chapter 10 of the book entitled "Computer Architecture", 2nd ed., by Caxton C. Foster, published by Van Nostrand, Reinhold company, 1976, That chapter, entitled "Very Large Computers" discusses among other techniques memory interleaving (which essentially is the fetching of multiple words simultaneously from independent memory modules); the instruction pre-fetch (look ahead), which is an instruction buffer memory which is loaded with the following instruction words when the bus memory system is not in use, and implies a second buffer or cache memory such as the pre-fetch technique described in U.S. Pat. No. 4,371,924, issued Feb. 1, 1983 to Marcus J. Schaefer et.al. which provides an excellent background for understanding a two-level hierarchy system and is hereby incorporated by reference; and the cache previously discussed.
One could properly assume, as the title to chapter 10, "Very Large Computers" , implies, tnat all of these techniques are substantially limited to large expensive architectures, and therefore are not suitable for solving the memory speed-up problems encountered in small compact and inexpensive systems.